SH7101 datasheet(378/486 Pages) RENESAS

378 / 486 page

12. Compare Match Timer (CMT)

Rev.2.00 Sep. 27, 2007 Page 344 of 448

REJ09B0394-0200

12.2

The CMT has the following registers. For details on register addresses and register states during

each processing, refer to section 18, List of Registers.

• Compare Match Timer Start Register (CMSTR)

• Compare Match Timer Control/Status Register_0 (CMCSR_0)

• Compare Match Timer Counter_0 (CMCNT_0)

• Compare Match Timer Constant Register_0 (CMCOR_0)

• Compare Match Timer Control/Status Register_1 (CMCSR_1)

• Compare Match Timer Counter_1 (CMCNT_1)

• Compare Match Timer Constant Register_1 (CMCOR_1)

12.2.1

Compare Match Timer Start Register (CMSTR)

CMSTR is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1

counters (CMCNT).

Bit

Bit Name

Initial

Value

R/W

Description

15 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

STR1

R/W

Count Start 1

This bit selects whether to operate or halt compare

match timer counter_1.

0: CMCNT_1 count operation halted

1: CMCNT_1 count operation

STR0

R/W

Count Start 0

This bit selects whether to operate or halt compare

match timer counter_0.

0: CMCNT_0 count operation halted

1: CMCNT_0 count operation

SH7101 Datasheet(PDF) 378 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 378 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL