SH7101 datasheet(291/486 Pages) RENESAS

291 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 257 of 448

REJ09B0394-0200

Bit

Bit Name

Initial

value

R/W

Description

POE0M1

POE0M0

R/W

POE0 mode 1, 0

These bits select the input mode of the

POE0 pin

00: Accept request on falling edge of

POE0 input

01: Accept request when

POE0 input has been sampled

for 16 P

φ/8 clock pulses, and all are low level.

10: Accept request when

POE0 input has been sampled

for 16 P

φ/16 clock pulses, and all are low level.

11: Accept request when

POE0 input has been sampled

for 16 P

φ/128 clock pulses, and all are low level.

Note:

The write value should always be 0.

Output Level Control/Status Register (OCSR): The output level control/status register (OCSR)

is a 16-bit readable/writable register that controls the enable/disable of both output level

comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins

become high impedance.

Bit

Bit Name

Initial

value

R/W

Description

OSF

R/(W)* Output Short Flag

This flag indicates that any one pair of the three pairs of

2 phase outputs compared have simultaneously

become low level outputs.

[Clearing condition]

• By writing 0 to OSF after reading an OSF = 1

[Setting condition]

• When any one pair of the three 2-phase outputs

simultaneously become low level

14 to 10

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7101 Datasheet(PDF) 291 Page - Renesas Technology Corp

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