SH7101 datasheet(288/486 Pages) RENESAS

288 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 254 of 448

REJ09B0394-0200

8.9.2

Pin Configuration

Table 8.44

Pin Configuration

Name

Abbreviation

I/O

Description

Port output enable input pins

POE0 to POE3

Input

Input request signals to make high-

current pins high-impedance state

Table 8.45 shows output-level comparisons with pin combinations.

Table 8.45

Pin Combinations

Pin Combination

I/O

Description

PE9/TIOC3B and PE11/TIOC3D

Output

All high-current pins are made high-impedance state

when the pins simultaneously output low-level for

longer than 1 cycle.

PE12/TIOC4A and PE14/TIOC4C

Output

All high-current pins are made high-impedance state

when the pins simultaneously output low-level for

longer than 1 cycle.

PE13/TIOC4B/

MRES and

PE15/TIOC4D/

IRQOUT

Output

All high-current pins are made high-impedance state

when the pins simultaneously output low-level for

longer than 1 cycle.

8.9.3

The POE has the two registers. The input level control/status register 1 (ICSR1) controls both

POE0 to POE3 pin input signal detection and interrupts. The output level control/status register

(OCSR) controls both the enable/disable of output comparison and interrupts.

Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1)

is a 16-bit readable/writable register that selects the

POE0 to POE3 pin input modes, controls the

enable/disable of interrupts, and indicates status.

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