3886 datasheet(210/380 Pages) RENESAS

210 / 380 page

3886 Group User’s Manual

APPLICATION

2-93

2.5 Multi-master I2C-BUS interface

➃ Reception of lower data

Confirm correct completion of communication at ➂ before receiving the lower data. After confirming

correct completion, clear the ACK bit (bit 6 of address 001616) to “0”, in which ACK is returned,

and set to the master receive mode. After that, write dummy data to the I2C data shift register

(address 001216).

When the MST bit (bit 7 of address 001416) is “0”, perform the error process explained as follows

and return to the process ➀.

When the last received bit (LRB bit; bit 0 of address 001416) is “1”, generate the STOP condition

and make the bus release, because the slave device specified on the I2C-BUS does not exist.

Fig. 2.5.22 Reception process of lower data

1(STOP condition)

AL (address 1416), bit 3 ?

MST (address 1416), bit 7 ?

0(ACK)

1(master)

S2(address 1616)

← 100001012

LRB (address 1416), bit0 ?

0(slave)

1(NACK)

1(detected)

0(not detected)

End

Re-transmission preparation

Error processing

S1(address 1416)

←101000002

S0(address 1216)

← 111111112

PIN (address 1416), bit 4 ?

0(transmission of RESTART

condition)

• Master receive mode set

Stop condition output

• Judgment of bus hold

• Judgment of arbitration lost detection

• ACK confirmation

• “ACK clock is used” select and

“ACK is returned” set

• Judgment of slave mode detection

• Dummy data to I2C data shift register write

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