3886 datasheet(222/380 Pages) RENESAS

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3886 Group User’s Manual

2-105

APPLICATION

2.5 Multi-master I2C-BUS interface

(5)

Process of after STOP condition generating

Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy

flag BB becomes “0” after generating the STOP condition in the master mode. Because the STOP

condition waveform might not be normally generated. Reading to the above registers does not have

the problem.

(6)

STOP condition input at 7th clock pulse

The SDA line may be held at LOW even if flag BB is set to “0” when all the following conditions are

satisfied:

•The STOP condition is input at the 7th clock pulse while receiving a slave address or data.

•The clock pulse is continuously input.

•In the slave mode

Countermeasure:

Write dummy data to the I2C data shift register or reset the ES0 bit in the S1D register (ES0 = “L”

→ ES0 = “H”) during a stop condition interrupt routine with flag BB = “0”.

Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is

set to “0”, the SDA pin becomes a general-purpose port ; so that the port must be set to input

mode or output “H”.

(7)

ES0 bit switch

In standard clock mode when SSC = “000102” or in high-speed clock mode, flag BB may switch to

“1” if ES0 bit is set to “1” when SDA is “L”.

Countermeasure:

Set ES0 to “1” when SDA is “H”.

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