3886 datasheet(305/380 Pages) RENESAS

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3886 Group User’s Manual

APPENDIX

3.1 Electrical characteristics

3-12

Note: The RESETOUT output goes “H” in synchronized with the rise of the

φ clock that is anywhere between a few cycles and 10-several cycles after RESET

input goes “H”.

Table 3.1.19 Timing requirements in memory expansion mode and microprocessor mode

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)

ONW input setup time

ONW input hold time

Data bus setup time

Data bus hold time

ONW input setup time

ONW input hold time

Data bus setup time

Data bus hold time

tsu (ONW-

φ)

th (

φ-ONW)

tsu (DB-

φ)

th (

φ-DB)

tsu (ONW-RD), tsu (ONW-WR)

th (RD-ONW), th (WR-ONW)

tsu (DB-RD)

th (RD-DB)

Limits

Parameter

Min.

Typ.

Max.

Symbol

Unit

–20

3.1.12 Switching characteristics in memory expansion mode and microprocessor mode

Table 3.1.20 Switching characteristics in memory expansion mode and microprocessor mode

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

AD15–AD8 delay time

AD7–AD0 delay time

AD15–AD8 valid time

AD7–AD0 valid time

SYNC delay time

SYNC valid time

Data bus delay time

Data bus valid time

RD pulse width, WR pulse width

(When one-wait is valid)

AD15–AD8 delay time

AD7–AD0 delay time

AD15–AD8 valid time

AD7–AD0 valid time

Data bus delay time

Data bus valid time

RESETOUT output delay time

RESETOUT output valid time (Note)

tC(

φ)

tWH(

φ)

tWL(

φ)

td(

φ-AH)

td(

φ-AL)

tV(

φ-AH)

tV(

φ-AL)

td(

φ-SYNC)

tV(

φ-SYNC)

td(

φ-DB)

tV(

φ-DB)

tWL(RD), tWL(WR)

td(AH-RD), td(AH-WR)

td(AL-RD), td(AL-WR)

tV(RD-AH), tV(WR-AH)

tV(RD-AL), tV(WR-AL)

td(WR-DB)

tV(WR-DB)

td(RESET-RESETOUT)

tV(

φ-RESETOUT)

Limits

Parameter

Min.

Typ.

Max.

Symbol

Unit

Test

conditions

Fig. 3.1.1

tC(XIN)–10

3tC(XIN)–10

tC(XIN)–35

tC(XIN)–40

200

100

2tC(XIN)

tC(XIN)–16

tC(XIN)–20

3.1.11 Timing requirements in memory expansion mode and microprocessor mode

Fig. 3.1.1 Circuit for measuring output switching characteristics (1)

Fig. 3.1.2 Circuit for measuring output switching characteristics (2)

Measurement output pin

100 pF

CMOS output

N-channel open-drain output

Measurement output pin

100 pF

1 k

Ω

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