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3886 Datasheet(PDF) 304 Page - Renesas Technology Corp

Part # 3886
Description  8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  380 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

3886 Datasheet(HTML) 304 Page - Renesas Technology Corp

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3886 Group User’s Manual
APPENDIX
3-11
3.1 Electrical characteristics
3.1.9 Switching characteristics
Table 3.1.15 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
0
Typ.
10
10
Max.
140
30
30
200
30
30
30
Symbol
Unit
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Test
conditions
Fig. 3.1.1
Fig. 3.1.2
Fig. 3.1.1
Table 3.1.16 Switching characteristics (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–240
tC(SCLK2)/2–240
0
Typ.
20
20
Max.
350
50
50
400
50
50
50
Symbol
Unit
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Test
conditions
Fig. 3.1.1
Fig. 3.1.2
Fig. 3.1.1
3.1.10 Switching characteristics for system bus interface
Table 3.1.17 Switching characteristics for system bus interface (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
ta(R-D)
tv(R-D)
tPLH(R-OBF)
Limits
ns
ns
ns
Parameter
Min.
Typ.
Max.
Symbol
Unit
0
80
30
150
Table 3.1.18 Switching characteristics for system bus interface (2)
(VCC =2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
ta(R-D)
tv(R-D)
tPLH(R-OBF)
Limits
ns
ns
ns
Parameter
Min.
Typ.
Max.
Symbol
Unit
0
130
85
300



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