3886 datasheet(302/380 Pages) RENESAS

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3886 Group User’s Manual

APPENDIX

3-9

3.1 Electrical characteristics

Table 3.1.12 Timing requirements (2)

(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Reset input “L” pulse width

Main clock input cycle time

Main clock input “H” pulse width

Main clock input “L” pulse width

Sub-clock input cycle time

Sub-clock input “H” pulse width

Sub-clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(XCIN)

tWH(XCIN)

tWL(XCIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tWH(INT)

tWL(INT)

Limits

XIN cycles

µs

Parameter

Min.

1000/(4.5VCC–8)

400/(4.5VCC–8)

500

230

Typ.

Max.

Symbol

Unit

Note : When bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when bit 6 of address 001A16 is “0” (UART).

tC(SCLK1)

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD-SCLK1)

th(SCLK1-RxD)

tC(SCLK2)

tWH(SCLK2)

tWL(SCLK2)

tsu(SIN2-SCLK2)

th(SCLK2-SIN2)

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “H” pulse width

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input setup time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input setup time

Serial I/O2 input hold time

2000

950

400

200

2000

950

400

300

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