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7480 Datasheet(PDF) 115 Page - Renesas Technology Corp

Part # 7480
Description  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
PDF  337 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7480 Datasheet(HTML) 115 Page - Renesas Technology Corp

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7480 Group and 7481 Group User's Manual
1-98
HARDWARE
1.13 Timer 1 and Timer 2
1.13.3 Basic Operations of Timer 1 and Timer 2
Basic operations of timer 1 and timer 2 are described below.
For details, refer to (1) Operations of each mode.
Count Sources
Timer 1 and timer 2 can select the following count sources with the timer 1 or 2 count source select bits
of the timer 1 or 2 mode register:
• f(XIN)/8
• f(XIN)/64
• f(XIN)/128
• f(XIN)/256
Writes to Timers
When ‘TL(0016 through FF16)’ is written to a timer, ‘TL’ is set in both the timer and the timer latch.
Note: A write to an operating timer causes the contents of the timer to be affected, so that the period from
the last underflow until the next underflow is undefined.
Reads from Timers
The contents of the timer can be read by a read operation.
Count Operations
The count operation (start/stop) of timer 1 or timer 2 is controlled by the timer 1 or 2 stop control bit of
the timer 1 or 2 mode register as follows:
• When the timer 1 or 2 stop control bit is set to ‘0’, the timer starts counting.
• When the timer 1 or 2 stop control bit is set to ‘1’, the timer stops counting.
In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count
source.
The timer 1 or 2 stop control bit is recognized during the HIGH time of the count source. When the count
has stopped, the count source cannot be accepted.
Reloading Timers
When a timer reaches ‘FF16’ in the count operation, an underflow occurs at the subsequent rising edge of
the count source, and the value decremented by 1 from the contents of the timer latch is reloaded to the
timer.
Timer Interrupt
At an underflow, the timer 1 or 2 interrupt request bit of interrupt request register 1 is set to ‘1’; then a
timer interrupt request is generated.
Table 1.13.1 lists the relation between timer count periods and values set to timer 1 and timer 2.



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