7480 datasheet(127/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-110

1.14 Serial I/O

HARDWARE

Overrun Error Flag (OE: bit 3)

This flag indicates the status of reading receive data.

• When the next receive data is stored completely in the receive shift register before the receive data

stored in the receive buffer register is read through, this flag is set to ‘1’.

• This flag is cleared to ‘0’ by any operations listed in Table 1.14.1.

This flag is valid in both clock synchronous serial I/O and UART.

Parity Error Flag (PE: bit 4)

This flag indicates the result of checking even or odd parity by hardware in UART.

• This flag is set to ‘1’ when the parity of the receive data differs from the predetermined parity.

• This flag is cleared to ‘0’ by any operation listed in Table 1.14.1.

This flag is valid only at parity enable in UART.

Framing Error Flag (FE: bit 5)

This flag indicates faults of frame synchronization in UART.

• When the stop bit of receive data is not received at the specified timing, this flag is set to ‘1’. Only

the first stop bit is tested and the second stop bit is not tested.

• This flag is cleared to ‘0’ by any operation listed in Table 1.14.1.

This flag is valid only in UART.

Summing Error Flag (SE: bit 6)

This flag indicates faults of serial I/O.

• When the overrun error, parity error or framing error occurs, this flag is set to ‘1’.

• This flag is cleared to ‘0’ by any operation listed in Table 1.14.1.

This flag is valid in both clock synchronous serial I/O and UART.

[Clearing Error Flag]

Error flags (bits 3 to 6) of the serial I/O status register are cleared to ‘0’ by any operation listed in

Table 1.14.1.

Table 1.14.1 Clearing Error Flags

Error Flag

Overrun Error Flag

Parity Error Flag

Framing Error Flag

Summing Error Flag

Dummy Data is Written to

Serial I/O Status Register

Set Serial I/O Enable Bit

to ‘0’

Set Receive Enable Bit

to ‘0’

Clearing Method

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