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7480 Datasheet(PDF) 131 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 131 Page - Renesas Technology Corp |
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131 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-114 1.14 Serial I/O HARDWARE 1.14.2 Clock Synchronous Serial I/O In clock synchronous serial I/O, the transmit operation of the transmitter (Note 1) and the receive operation of the receiver (Note 2) are performed simultaneously, synchronizing with the synchronous clock used for transferring, which is generated by the clock control circuit. Notes 1: Synchronized with falling edges of the synchronous clock, data is transmitted from the TxD pin of the transmitter by the bit. 2: Synchronized with rising edges of the synchronous clock, data is received from the RxD pin of the receiver by the bit. Clock synchronous serial I/O is selected by setting the serial I/O mode selection bit of the serial I/O control register to ‘1’. Data Communication • Half-duplex communication: one of the two communicating microcomputers operates only as a transmitter and the other only as a receiver at a time or vice versa. • Full-duplex communication: both of the two communicating microcomputers operate simultaneously as transmitter and receiver. Synchronous Clock A synchronous clock is selected by the serial I/O synchronous clock selection bit of the serial I/O control register as follows: • 0: BRG output/4 • 1: External clock input to the SCLK pin For the BRG output, refer to (5) Baud Rate Generator (BRG) in Section 1.14.1. When a clock synchronous serial I/O communication is carried out between two microcomputers, the synchronous clock is normally selected as follows: • Microcomputer 1 clears the serial I/O synchronous clock selection bit to ‘0’, and 8 synchronous clock pulses, generated by writing to the transmit buffer register, are output from the SCLK pin. • Microcomputer 2 selects the external clock and inputs the pulses outputted from microcomputer 1 to the SCLK pin. This is the synchronous clock. Note: When an external clock is selected as the synchronous clock: Perform the following operations while the SCLK pin input is HIGH during data transmission: • Write ‘1’ to the transmit enable bit • Write transmit data to the transmit buffer register The shift operations of the transmit shift register and the receive shift register are performed while the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8 cycles when an external clock is selected as the synchronous clock. The synchronous clock automatically stops after 8 synchronous clock pulses generated when the BRG output/4 is selected as the synchronous clock. |
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