7480 datasheet(132/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-115

1.14 Serial I/O

HARDWARE

Data Transfer Rate (Baud Rate)

In clock synchronous serial I/O, the data transfer rate (baud rate), which is the frequency of the synchronous

clock, is calculated by the following formulas:

• When the serial I/O synchronous clock selection bit is ‘0’.

(BRG output/4 is selected as the synchronous clock)

Baud rate [bps] =

Notes 1: BRG count source selection bit of the serial I/O control register is as follows:

• ‘0’: Division ratio is 4

• ‘1’: Division ratio is 16.

2: The value written to the baud rate generator (0016 to FF16).

• When the serial I/O synchronous clock selection bit is ‘1’

(an external clock input is selected as the synchronous clock):

Baud rate [bps] = the external clock input frequency from the SCLK pin

Output of SRDY Signal

In clock synchronous serial I/O, the output level of the SRDY pin changes from HIGH to LOW by writing

to the transmit buffer register when the SRDY output enable bit of serial I/O control register is ‘1’. The

completion of the serial I/O communication preparation is signaled to the external by the SRDY output. Also,

the SRDY pin returns to the HIGH state at the first falling edge of the synchronous clock.

Note: Set the transmit enable bit to ‘1’ as well as the receive enable bit and the SRDY output enable bit

of the serial I/O control register when the receiver outputs the SRDY signal while the external clock

is selected as the synchronous clock.

Starting of Transmission and Reception

• When the BRG output/4 is selected as the synchronous clock:

Transmitting and receiving starts when a write to the transmit buffer register occurs.

Normally, communication is started after the completion of communication preparation of the target unit

is recognized with the SRDY signal.

• When the external clock is selected as the synchronous clock:

Transmitting and receiving starts when input to the external clock starts.

When data is written to the transmit buffer register, the output level of the SRDY pin changes from HIGH

to LOW and informs the target unit of the completion of communication preparation.

f(XIN)

Division ratio (Note 1)

× (BRG setting value (Note 2) + 1) × 4

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