AT91SAM9G20 datasheet(90/832 Pages) ATMEL

90 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup

time.

After this time, the processor clock is released at Slow Clock and all the other signals remain

valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released

and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the

NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.

When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi-

ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown.

VDDBU only activates the backup_nreset signal.

The backup_nreset must be released so that any other reset can be generated by VDDCORE

(Main Supply POR output).

Figure 14-4 shows how the General Reset affects the reset signals.

Figure 14-4. General Reset State

SLCK

periph_nreset

proc_nreset

Backup Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

Startup Time

MCK

Processor Startup

= 3 cycles

backup_nreset

Any

Freq.

RSTTYP

XXX

0x0 = General Reset

XXX

Main Supply

POR output

BMS Sampling

AT91SAM9G20 Datasheet(PDF) 90 Page - ATMEL Corporation