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AT91SAM9G20 Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT91SAM9G20 Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 832 page ![]() 25 6384D–ATARM–04-May-09 AT91SAM9G20 Preliminary 9.2 Reset Controller • Based on two Power-on-Reset cell – one on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output – Allows shaping a reset signal for the external devices 9.3 Shutdown Controller • Shutdown and Wake-Up logic – Software programmable assertion of the SHDWN pin – Deassertion Programmable on a WKUP pin level change or on alarm 9.4 Clock Generator • Embeds a Low Power 32768 Hz Slow Clock Oscillator and a Low power RC oscillator selectable with OSCSEL signal – Provides the permanent Slow Clock SLCK to the system • Embeds the Main Oscillator – Oscillator bypass feature – Supports 3 to 20 MHz crystals • Embeds 2 PLLs – The PLL A outputs 400-800 MHz clock – The PLL B outputs 100 MHz clock – Both integrate an input divider to increase output accuracy – PLL A and PLL B embed their own filters |
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