AT91SAM9G20 datasheet(46/832 Pages) ATMEL

46 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

pipeline. If the instruction is not executed, for example because a branch occurs while it is in the

pipeline, the abort does not take place.

The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the

problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction

caused a Prefetch Abort.

A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until

the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for

example because a branch occurs while it is in the pipeline, the breakpoint does not take place.

11.3.8

ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition

code field (bits[31:28]).

For further details, see the ARM Technical Reference Manual, ARM ref. DDI0198B.

Table 11-2 gives the ARM instruction mnemonic list.

Table 11-2.

ARM Instruction Mnemonic List

Mnemonic

Operation

Mnemonic

Operation

MOV

Move

MVN

Move Not

ADD

Add

ADC

Add with Carry

SUB

Subtract

SBC

Subtract with Carry

RSB

Reverse Subtract

RSC

Reverse Subtract with Carry

CMP

Compare

CMN

Compare Negated

TST

Test

TEQ

Test Equivalence

AND

Logical AND

BIC

Bit Clear

EOR

Logical Exclusive OR

ORR

Logical (inclusive) OR

MUL

Multiply

MLA

Multiply Accumulate

SMULL

Sign Long Multiply

UMULL

Unsigned Long Multiply

SMLAL

Signed Long Multiply Accumulate

UMLAL

Unsigned Long Multiply

Accumulate

MSR

Move to Status Register

MRS

Move From Status Register

Branch

Branch and Link

Branch and Exchange

SWI

Software Interrupt

LDR

Load Word

STR

Store Word

LDRSH

Load Signed Halfword

LDRSB

Load Signed Byte

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