AT91SAM9G20 datasheet(54/832 Pages) ATMEL

54 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide

whether all, half or none is written back to memory.

DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see

Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM).

The DCache supports write-through and write-back cache operations, selected by memory

region using the C and B bits in the MMU translation tables.

The DCache contains an eight data word entry, single address entry write-back buffer used to

hold write-back data for cache line eviction or cleaning of dirty cache lines.

The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and

Write Buffer operations are closely connected as their configuration is set in each section by the

page descriptor in the MMU translation table.

11.6.2.2

Write Buffer

The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address

buffer. The write buffer is used for all writes to a bufferable region, write-through region and

write-back region. It also allows to avoid stalling the processor when writes to external memory

are performed. When a store occurs, data is written to the write buffer at core speed (high

speed). The write buffer then completes the store to external memory at bus speed (typically

slower than the core speed). During this time, the ARM9EJ-S processor can preform other

tasks.

DCache and Write Buffer support write-back and write-through memory regions, controlled by C

and B bits in each section and page descriptor within the MMU translation tables.

11.6.2.3

Write-though Operation

When a cache write hit occurs, the DCache line is updated. The updated data is then written to

the write buffer which transfers it to external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in

the write buffer which transfers it to external memory.

11.6.2.4

Write-back Operation

When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its

contents are not up-to-date with those in the external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in

the write buffer which transfers it to external memory.

AT91SAM9G20 Datasheet(PDF) 54 Page - ATMEL Corporation