AT91SAM9G20 datasheet(91/832 Pages) ATMEL

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6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

14.3.4.2

Wake-up Reset

The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output

is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow-

ers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled

during 3 Slow Clock cycles, depending on the requirements of the ARM processor.

At the end of this delay, the processor and other reset signals rise. The field RSTTYP in

RSTC_SR is updated to report a Wake-up Reset.

The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is

backed-up, the programmed number of cycles is applicable.

When the Main Supply is detected falling, the reset signals are immediately asserted. This tran-

sition is synchronous with the output of the Main Supply POR.

Figure 14-5. Wake-up State

14.3.4.3

User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in

RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-

ior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset

and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle

processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

SLCK

periph_nreset

proc_nreset

Main Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 4 cycles (ERSTL = 1)

MCK

Processor Startup

= 3 cycles

backup_nreset

Any

Freq.

Resynch.

2 cycles

RSTTYP

XXX

0x1 = WakeUp Reset

XXX

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