AT91SAM9G20 datasheet(26/832 Pages) ATMEL

26 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

Figure 9-2.

Clock Generator Block Diagram

9.5

Power Management Controller

•Provides:

– the Processor Clock PCK

– the Master Clock MCK, in particular to the Matrix and the memory interfaces.The

MCK divider can be 1,2,4,6

– the USB Device Clock UDPCK

– independent peripheral clocks, typically at the frequency of MCK

– 2 programmable clock outputs: PCK0, PCK1

• Five flexible operating modes:

– Normal Mode, processor and peripherals running at a programmable frequency

– Idle Mode, processor stopped waiting for an interrupt

– Slow Clock Mode, processor and peripherals running at low frequency

– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,

processor stopped waiting for an interrupt

– Backup Mode, Main Power Supplies off, VDDBU powered by a battery

On Chip

RC OSC

Power

Management

Controller

XIN

XOUT

Slow Clock

SLCK

Main Clock

MAINCK

PLLA Clock

PLLACK

Control

Status

PLL and

Divider B

PLLB Clock

PLLBCK

XIN32

XOUT32

Slow Clock

Oscillator

Main

Oscillator

PLL and

Divider A

Clock Generator

OSCSEL

AT91SAM9G20 Datasheet(PDF) 26 Page - ATMEL Corporation

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