AT91SAM9G20 datasheet(52/832 Pages) ATMEL

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6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

fied Virtual Address), the access control logic determines if the access is permitted and outputs

the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU

signals the CPU core to abort.

If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked

to retrieve the translation information from the translation table in physical memory.

11.5.3

Translation Table Walk Hardware

The translation table walk hardware is a logic that traverses the translation tables located in

physical memory, gets the physical address and access permissions and updates the TLB.

The number of stages in the hardware table walking is one or two depending whether the

address is marked as a section-mapped access or a page-mapped access.

There are three sizes of page-mapped accesses and one size of section-mapped access. Page-

mapped accesses are for large pages, small pages and tiny pages. The translation process

always begins with a level one fetch. A section-mapped access requires only a level one fetch,

but a page-mapped access requires an additional level two fetch. For further details on the

MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

11.5.4

MMU Faults

The MMU generates an abort on the following types of faults:

• Alignment faults (for data accesses only)

• Translation faults

• Domain faults

• Permission faults

The access control mechanism of the MMU detects the conditions that produce these faults. If

the fault is a result of memory access, the MMU aborts the access and signals the fault to the

CPU core.The MMU retains status and address information about faults generated by the data

accesses in the data fault status register and fault address register. It also retains the status of

faults generated by instruction fetches in the instruction fault status register.

The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and

the domain number of the aborted access when it happens. The fault address register (register 6

in CP15) holds the MVA associated with the access that caused the Data Abort. For further

details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

AT91SAM9G20 Datasheet(PDF) 52 Page - ATMEL Corporation