AT91SAM9G20 datasheet(93/832 Pages) ATMEL

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6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field

ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field

RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in

RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in

Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is

left. No other software reset can be performed while the SRCMP bit is set, and writing any value

in RSTC_CR has no effect.

Figure 14-7. Software Reset

14.3.4.5

Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock

cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in

WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST

line is also asserted, depending on the programming of the field ERSTL. However, the

resulting low level on NRST does not result in a User Reset state.

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a

processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog

Reset, and the Watchdog is enabled by default and with a period set to a maximum.

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PROCRST=1

Write RSTC_CR

NRST

(nrst_out)

if EXTRST=1

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x3 = Software Reset

Resynch.

1 cycle

SRCMP in RSTC_SR

AT91SAM9G20 Datasheet(PDF) 93 Page - ATMEL Corporation

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