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AT91SAM9G20 Datasheet(PDF) 18 Page - ATMEL Corporation |
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AT91SAM9G20 Datasheet(HTML) 18 Page - ATMEL Corporation |
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18 / 832 page  18 6384D–ATARM–04-May-09 AT91SAM9G20 Preliminary – USART4 Transmit Channel – USART3 Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC Transmit Channel – TWI Receive Channel – DBGU Receive Channel – USART5 Receive Channel – USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel – MCI Transmit/Receive Channel 7.4 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit –Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins |
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