AT91SAM9G20 datasheet(14/832 Pages) ATMEL

14 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

I/O Line Considerations

6.1

JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left uncon-

nected for normal operations.

The NTRST signal is described in the Reset Pins paragraph.

All the JTAG signals are supplied with VDDIOP.

6.2

Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-

nent pull-down resistor of about 15 k

Ω to GNDBU, so that it can be left unconnected for normal

operations. Driving this line at a high level leads to unpredictable results.

This pin is supplied with VDDBU.

6.3

Reset Pins

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven

with voltage at up to VDDIOP.

NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the

processor.

As the product integrates power-on reset cells, which manages the processor and the JTAG

reset, the NRST and NTRST pins can be left unconnected.

The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k

Ω minimum to

VDDIOP.

The NRST signal is inserted in the Boundary Scan.

6.4

PIO Controllers

All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers inte-

grate a programmable pull-up resistor of 75 k

Ωtypical with the exception of P4 - P31. For details,

refer to the section “AT91SAM9G20 Electrical Characteristics”. Programming of this pull-up

resistor is performed independently for each I/O line through the PIO Controllers.

6.5

I/O Line Drive Levels

The PIO lines drive current capability is described in the DC Characteristics section of the prod-

uct datasheet.

6.6

Shutdown Logic Pins

The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is

no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than

Ω. The resistor value is calculated according to the regulator enable implementation and the

SHDN level.

AT91SAM9G20 Datasheet(PDF) 14 Page - ATMEL Corporation

AT91SAM9G20 Datasheet(HTML) 14 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL