AT91SAM9G20 datasheet(92/832 Pages) ATMEL

92 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

When the processor reset signal is released, the RSTTYP field of the Status Register

(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

T h e

NRST

M a nag er

gu ara n te es

tha t

the

NRST

line

asse rte d

fo r

EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-

ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low

externally, the internal reset lines remain asserted until NRST actually rises.

Figure 14-6. User Reset State

14.3.4.4

Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These

commands are performed by writing the Control Register (RSTC_CR) with the following bits at

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory

system, and, in particular, the Remap Command. The Peripheral Reset is generally used for

debug purposes.

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field

ERSTL in the Mode Register (RSTC_MR).

The software reset is entered if at least one of these bits is set by the software. All these com-

mands can be performed independently or simultaneously. The software reset lasts 3 Slow

Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is

detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-

chronously to SLCK.

SLCK

periph_nreset

proc_nreset

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup

= 3 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any

XXX

Resynch.

2 cycles

0x4 = User Reset

AT91SAM9G20 Datasheet(PDF) 92 Page - ATMEL Corporation

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