AT91SAM9G20 datasheet(22/832 Pages) ATMEL

22 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

Refer to the memory map in Figure 8-1 on page 19.

8.2.1

External Bus Interface

• Integrates three External Memory Controllers

– Static Memory Controller

– SDRAM Controller

– ECC Controller

• Additional logic for NAND Flash

• Full 32-bit External Data Bus

• Up to 26-bit Address Bus (up to 64MBytes linear)

• Up to 8 chip selects, Configurable Assignment:

– Static Memory Controller on NCS0

– SDRAM Controller or Static Memory Controller on NCS1

– Static Memory Controller on NCS2

– Static Memory Controller on NCS3, Optional NAND Flash support

– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support

– Static Memory Controller on NCS6-NCS7

8.2.2

Static Memory Controller

• 8-, 16- or 32-bit Data Bus

• Multiple Access Modes supported

– Byte Write or Byte Select Lines

– Asynchronous read in Page Mode supported (4- up to 32-byte page size)

• Multiple device adaptability

– Compliant with LCD Module

– Control signals programmable setup, pulse and hold time for each Memory Bank

• Multiple Wait State Management

– Programmable Wait State Generation

– External Wait Request

– Programmable Data Float Time

• Slow Clock mode supported

8.2.3

SDRAM Controller

• Supported devices

– Standard and Low-power SDRAM (Mobile SDRAM)

• Numerous configurations supported

– 2K, 4K, 8K Row Address Memory Parts

– SDRAM with two or four Internal Banks

– SDRAM with 16- or 32-bit Datapath

• Programming facilities

– Word, half-word, byte access

– Automatic page break when Memory Boundary has been reached

AT91SAM9G20 Datasheet(PDF) 22 Page - ATMEL Corporation

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