AT91SAM9G20 datasheet(42/832 Pages) ATMEL

42 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

Minimum interrupt latency is maintained across both ARM state and Java state. Since byte

codes execution can be restarted, an interrupt automatically triggers the core to switch from

Java state to ARM state for the execution of the interrupt handler. This means that no special

provision has to be made for handling interrupts while executing byte codes, whether in hard-

ware or in software.

11.3.6

ARM9EJ-S Operating Modes

In all states, there are seven operation modes:

• User mode is the usual ARM program execution state. It is used for executing most

application programs

• Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data

transfer or channel process

• Interrupt (IRQ) mode is used for general-purpose interrupt handling

• Supervisor mode is a protected mode for the operating system

• Abort mode is entered after a data or instruction prefetch abort

• System mode is a privileged user mode for the operating system

• Undefined mode is entered when an undefined instruction exception occurs

Mode changes may be made under software control, or may be brought about by external inter-

rupts or exception processing. Most application programs execute in User Mode. The non-user

modes, known as privileged modes, are entered in order to service interrupts or exceptions or to

access protected resources.

11.3.7

ARM9EJ-S Registers

The ARM9EJ-S core has a total of 37 registers.

• 31 general-purpose 32-bit registers

• 6 32-bit status registers

Table 11-1 shows all the registers in all modes.

Table 11-1.

ARM9TDMI Modes and Registers Layout

User and

System Mode

Supervisor

Mode

Abort Mode

Undefined

Mode

Interrupt

Mode

Fast Interrupt

Mode

R8_FIQ

R9_FIQ

R10R10

R10

R10_FIQ

R11R11

R11

R11_FIQ

AT91SAM9G20 Datasheet(PDF) 42 Page - ATMEL Corporation

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