AT91SAM9G20 datasheet(94/832 Pages) ATMEL

94 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset

controller.

Figure 14-8. Watchdog Reset

14.3.5

Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources,

given in descending order:

• Backup Reset

• Wake-up Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the

proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state.

– The NRST has no effect.

• When in Watchdog Reset:

– The processor reset is active and so a Software Reset cannot be programmed.

– A User Reset cannot be entered.

Only if

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x2 = Watchdog Reset

AT91SAM9G20 Datasheet(PDF) 94 Page - ATMEL Corporation

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