AT91SAM9G20 datasheet(53/832 Pages) ATMEL

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6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

11.6

Caches and Write Buffer

The ARM926EJ-S contains a 32 KB Instruction Cache (ICache), a 32 KB Data Cache (DCache),

and a write buffer. Although the ICache and DCache share common features, each still has

some specific mechanisms.

The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged

using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty

bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache

pollution control, and line replacement.

A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly

known as wrapping. This feature enables the caches to perform critical word first cache refilling.

This means that when a request for a word causes a read-miss, the cache performs an AHB

access. Instead of loading the whole line (eight words), the cache loads the critical word first, so

the processor can reach it quickly, and then the remaining words, no matter where the word is

located in the line.

The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7

(cache operations) and CP15 register 9 (cache lockdown).

11.6.1

Instruction Cache (ICache)

The ICache caches fetched instructions to be executed by the processor. The ICache can be

enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.

When the MMU is enabled, all instruction fetches are subject to translation and permission

checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are

made and the physical address is flat-mapped to the modified virtual address. With the MVA use

disabled, context switching incurs ICache cleaning and/or invalidating.

When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see

Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM).

On reset, the ICache entries are invalidated and the ICache is disabled. For best performance,

ICache should be enabled as soon as possible after reset.

11.6.2

Data Cache (DCache) and Write Buffer

ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band-

width and latency on data access performance. The operations of DCache and write buffer are

closely connected.

11.6.2.1

DCache

The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission

and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data

accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are

noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All

addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating

every time a context switch occurs.

The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and

uses it when writing modified lines back to external memory. This means that the MMU is not

involved in write-back operations.

Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other

one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the

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