AT91SAM9G20 datasheet(44/832 Pages) ATMEL

44 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see

the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).

11.3.7.1

Status Registers

The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The

program status registers:

• hold information about the most recently performed ALU operation

• control the enabling and disabling of interrupts

• set the processor operation mode

Figure 11-2. Status Register Format

Figure 11-2 shows the status register format, where:

• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags

• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic

instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve

DSP operations.

The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by

an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the

status of the Q flag.

• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:

– J = 0: The processor is in ARM or Thumb state, depending on the T bit

– J = 1: The processor is in Jazelle state.

• Mode: five bits to encode the current processor mode

11.3.7.2

Exceptions

Exception Types and Priorities

The

ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-

leged mode. The types of exceptions are:

• Fast interrupt (FIQ)

• Normal interrupt (IRQ)

• Data and Prefetched aborts (Abort)

• Undefined instruction (Undefined)

• Software interrupt and Reset (Supervisor)

NZ C V Q

F T

Mode

Reserved

Mode bits

Thumb state bit

FIQ disable

IRQ disable

Jazelle state bit

Reserved

Sticky Overflow

Overflow

Carry/Borrow/Extend

Zero

Negative/Less than

31 30 29 28 27

7 6 5

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