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ST7637 Datasheet(PDF) 31 Page - Sitronix Technology Co., Ltd. |
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ST7637 Datasheet(HTML) 31 Page - Sitronix Technology Co., Ltd. |
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31 / 210 page ![]() ST7637 Ver 1.6 31/210 2009/03 7.3 ACCESS TO DDRAM AND INTERNAL REGISTERS ST7637 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Figure 7.3-1 illustrates these relations. In 80-series interface mode: N Dummy D (N ) D (N +1) MPU signal A 0 DATA Internal signals ADDRESS COUNTER /RD N D (N ) D (N +1) D (N +2) D (N +3) INTERNAL LATCH Read Operation /WR /WR /RD D (N ) D (N +1) D (N +2) Figure 7.3-1 |
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