ST7637 datasheet(46/210 Pages) SITRONIX

46 / 210 page

ST7637

Ver 1.6

46/210

2009/03

7.8

POWER LEVEL DEFINITION

7.8.1.

Power ON/OFF SEQUENCE

NOTE: VDDI=VDD, VDD1; VDDA=VDD2, VDD3, VDD4, VDD5

During power off, if LCD is in the Sleep Out mode, VDDA and VDDI must be powered down minimum 120msec after /RST

has been released.

During power off, if LCD is in the Sleep In mode, VDDI or VDDA can be powered down minimum 0msec after /RST has

been released.

/CS can be applied at any timing or can be permanently grounded. /RST has priority over /CS.

If /RST line is not held stable by host during Power On Sequence as defined in Sections case1 and case2, then it will be

necessary to apply a Hardware Reset (/RST) after Host Power On Sequence is complete to ensure correct operation.

Otherwise function is not guaranteed.

The power on/off sequence is illustrated below:

Case 1 – /RST line is held High or Unstable by Host at Power On

If /RST line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDDA

and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this

hardware reset.

Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.

Case 2 – /RST line is held Low by host at Power On

If /RST line is held Low (and stable) by the host during Power On, then the /RST must be held low for minimum 10

µsec

after both VDDA and VDDI have been applied.

ST7637 Datasheet(PDF) 46 Page - Sitronix Technology Co., Ltd.