AS3524 datasheet(67/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 45 NAF data register

Name

Base

Default

NAFData

AS3525_NAND_FLASH_BASE

0x0000

Data Register

Offset 0x000C

The NAFData register offers unbuffered access to the data bus of the NAND flash

device.

Bit

Bit Name

Default

Access

Bit Description

15:0

NAFData

0x01

R/W

For X8 devices (8-bit data bus) only bits 7:0 are relevant, other

bits are ignored

For X16 devices (16-bit data bus) all are relevant

Table 46 NAF mode register

Name

Base

Default

NAFMode

AS3525_NAND_FLASH_BASE

0x00

Mode register

Offset 0x0010

The NAFMode register controls NAND flash read/write/erase procedures.

Bit

Bit Name

Default

Access

Bit Description

write protection

0x0

R/W

Used to control ‘command latch enable’

0: output ‘naf_cle’ is set to ‘0’

1: output ‘naf_cle’ is set to ‘1’ (Command Latch Cycle)

6:5

Ecc [1:0]

0x0

R/W

controls ‘address latch enable’

0: output ‘naf_ale’ is set to ‘0’

1: output ‘naf_ale’ is set to ‘1’ (Address Latch Cycle)

0x0

R/W

0: power off (all output enable signals are turned off)

1: power on

0x0

R/W

always ‘0’

power_on

0x0

R/W

0: power off (all output enable signals are turned off)

1: power on

ale

0x0

R/W

controls ‘address latch enable’

0: output ‘naf_ale’ is set to ‘0’

1: output ‘naf_ale’ is set to ‘1’ (Address Latch Cycle)

Cle

0x0

R/W

controls ‘command latch enable’

0: output ‘naf_cle’ is set to ‘0’

1: output ‘naf_cle’ is set to ‘1’ (Command Latch Cycle)

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