AS3524 datasheet(5/124 Pages) AMSCO

5 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

5.3.12

DBOP - Data Block Output Port ......................................................................................................... 73

5.3.13

UART – Universal Asynchronous Receiver/Transmitter.................................................................... 83

5.3.14

CGU - Clock generation unit .............................................................................................................. 90

5.3.15

CCU - Chip Control Unit .................................................................................................................. 104

PINOUT AND PACKAGING ...............................................................................109

6.1

Package Variants.......................................................................................................................................... 109

6.2

CTBGA180 Package Drawings ................................................................................................................... 109

6.2.1

Marking ............................................................................................................................................. 109

6.2.2

CTBGA180 Package Ball-out ........................................................................................................... 110

6.2.3

CTBGA180 Ball List ........................................................................................................................ 110

6.3

Pad Cell Description..................................................................................................................................... 118

6.3.1

Digital Pads ....................................................................................................................................... 118

APPENDIX ..........................................................................................................119

7.1

Memory MAP ............................................................................................................................................... 119

7.2

Register definitions....................................................................................................................................... 121

7.2.1

Base Address definitions................................................................................................................... 121

ORDERING INFORMATION ...............................................................................122

DISCLAIMER ......................................................................................................123

CONTACT INFORMATION.................................................................................123

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