AS3524 datasheet(59/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

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Revision 1.11

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Table 40 I2S output interrupt clear register

Name

Base

Default

I2SOUT_CLEAR

AS3525_I2SOUT_BASE

0x00

Interrupt clear register

Offset: 0x0010

The interrupt clear register is a write-only register. The corresponding static status

bit can be cleared by writing a 1 to the corresponding bit in the clear register. All

other interrupt flags are level interrupts depending on the status of the FIFO. The

bits are de-asserted depending on the FIFO controller.

Bit

Bit Name

Default

Access

Bit Description

reserved

I2SOUT_clear_poer

Clear POP error interrupt flag

5:1

reserved

I2SOUT_clear_puer

Clear PUSH error interrupt flag

I2SOUT_DATA

The I2SOUTIF provides two 32 bit wide data registers. The registers are used to store the audio samples before they are written to the FIFO. The

registers can be used in different modes depending on the setting of the I2SOUT_CONTROL register.

Basically, there are four ways to fill the FIFO.

The processor can provide

•

two 18 bit audio samples, one for each channel (R,L). The values are written to I2SOUT_DATA.

•

two 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SOUT_DATA

•

one 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the

I2SOUT_DATA.

•

one 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the

I2SOUT_DATA.

In 18 bit stereo mode the data in I2SOUT_DATA is interpreted either as left or right audio value. The stereo18_status bit in the I2SOUT_STATUS

The I2S Output Signals

The following specifications signals are given:

•

Data are valid at the rising edge of I2SO_SCLK.

•

The MSB is left justified to the I2S frame identification (I2SO_LRCK). According to standard I2S definition, a delay of

one clock cycle between transition of I2SO_LRCK and the data MSB is used.

The timing diagram of the I2S interface signals for 18bit and 16bit DAC is shown below.

Left Channel

Right Channel

I2SO_LRCK

I2SO_SCLK

I2SO_SDATA

16 bit

I2SO_SDATA

18 bit

I2SO_MCLK

period(fsaudio) / 2

Figure 27 - I2S output timing diagram

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