AS3524 datasheet(68/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 47 NAF status register

Name

Base

Default

NAFStatus

AS3525_NAND_FLASH_BASE

Status Register

Offset 0x0014

The NAFStatus register contains information on the internal status.

Bit

Bit Name

Defau

Access

Bit Description

fifo_error

0x0

FIFO error signal

0: if FIFO is reset

1: if FIFO contains 36 words and FIFO push(write) has

occurred or when FIFO contains 0 words and a FIFO pop(read)

has occurred. The FIFO error will lock the FIFO and has to be

reset by a reset of the FIFO (by setting NAFControl register bit

1 to ‘1’)

fifo_full

0x0

FIFO full signal

0: if FIFO contains less than 36 words

1: if FIFO contains 36 words

fifo_almost_full

0x0

FIFO almost_full signal

0: if FIFO contains less than 32 words

1: if FIFO contains more than or equal 32 words

fifo_almost_empty

0x0

FIFO almost_empty signal

0: if FIFO contains more than 4 words

1: if FIFO contains less than or equal 4 words

fifo_empty

0x0

FIFO empty signal

0: if FIFO contains more than 0 words

1: = when FIFO contains 0 words

strobe_ready

0x0

read/write strobe ready signal

0: if read/write strobe ‘0’ (strobe active)

1: if read/write strobe ‘1’ (strobe inactive)

flash_ready

0x0

synchronised NAND flash ready signal

0: if synchronised input ‘naf_busy_in_n’ is ‘0’ (busy)

1: if synchronised input ‘naf_busy_in_n’ is ‘1’ (ready)

got_fifo_error

0x0

FIFO error indication (edge triggered)

0: if bit 6 of NAFClear register is set to ‘1’

1: if FIFO contains 36 words and FIFO push(write) occurs or

when FIFO contains 0 words and a FIFO pop(read) occurs.

got_fifo_full

0x0

FIFO full indication (edge triggered)

0: if bit 5 of NAFClear register is set to ‘1’

1: if FIFO contains 36.

got_fifo_high

0x0

FIFO high indication (edge triggered)

0: if bit 4 of NAFClear register is set to ‘1’

1: if FIFO gets full (36 words) or changes from 31 to 32 words

(and when the NAFWords register is greater than 32).

Note: When this bit gets ‘1’ during ‘Page Read’ mode, a new

FIFO burst read of up to 32 words is possible.

got_fifo_low

0x0

FIFO low indication (edge triggered)

0: if bit 3 of NAFClear register is set to ‘1’

1: if FIFO gets empty or changes from 5 to 4 words (and when

the NAND Flash requires more than 32 bytes/halfwords).

Note: When this bit gets ‘1’ during ‘Page Programming’ mode,

a new FIFO burst write of up to 32 words is possible

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