AS3524 datasheet(98/124 Pages) AMSCO

98 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 26 Peripheral Clock Controller Register

Name

Base

Default

CGU_PERI

AS3525_CGU_BASE

0x0F800000

Peripheral clock controller register

Offset0x14

This register allows setting the peripheral clocks.

Bit

Bit Name

Default

Access

Bit Description

MBIST_EN

R/W

memory bist manager clock enable

EXTMEM_EN

R/W

external memory clock enable

EXTMEMIF_EN

R/W

external memory AHB IF clock enable

1TRAM_EN

R/W

1TRAM controller AHB IF clock enable

ROM_EN

R/W

ROM AHB IF clock enable

VIC_EN

R/W

vectored interrupt controller AHB IF clock enable

DMAC_EN

R/W

DMA controller AHB IF clock enable

USB_EN

R/W

USB controller AHB IF clock enable

I2SO_APB_EN

R/W

I2Sout APB IF clock enable

I2SI_APB_EN

R/W

I2Sin APB IF clock enable

I2C_EN

R/W

I2C master/slave APB IF clock enable

I2C_AUDIO_EN

R/W

I2C audio APB IF clock enable

GPIO_EN

R/W

general purpose IO APB IF clock enable

SDMCI_EN

R/W

secure digital/multimedia APB IF clock enable

NANDFLASH_EN

R/W

NAND flash/Smart Media APB IF clock enable

UART_EN

R/W

UART APB IF clock enable

WDOCNT_EN

R/W

watchdog counter clock enable

WDOIF_EN

R/W

watchdog timer module APB IF clock enable

SSP_EN

R/W

synchronous serial port APB IF clock enable

TIMER1_EN

R/W

timer module timer1 clock enable

TIMER2_EN

R/W

timer module timer2 clock enable

TIMERIF_EN

R/W

timer module APB IF clock enable

PCLK_DIV1_SEL

R/W

division ratio div1 (AHB/APB clock) => div1 = 1/(pclk_div1_sel

+ 1)

5:2

PCLK_DIV0_SEL

[3:0]

0x0

R/W

division ratio div0 (ext. memory clock) => div0 =

1/(pclk_div0_sel + 1)

1:0

PCLK_SEL[1:0]

0x0

R/W

clkin select

b’00: clk_main

b’01: plla_fout

b’10: pllb_fout

b’11: fclk

CAUTION: Clock gating takes effect immediately! Software must assure that all transactions to/from the module are finished

before the clock is disabled.

CAUTION: The peripheral clock must not exceed 65 MHz. The software must assure that requirement.

Note:

f(clk_extmem) := f(clkin) * div0;

f(pclk) := f(clkin) * div0 * div1;

AS3524 Datasheet(PDF) 98 Page - ams AG

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