AS3524 datasheet(102/124 Pages) AMSCO

102 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

102

- 124

Table 34 Memory Stick (MS) Clock Controller Register

Name

Base

Default

CGU_MS

AS3525_CGU_BASE

0x00

MS Clock Controller Register

Offset: 0x34

This register allows setting the MS interface clocks.

Bit

Bit Name

Default

Access

Bit Description

MSIF_CLK_EN

R/W

MS APB IF clock enable

MS_CLK_EN

R/W

MS IF clock enable (20/40MHz domain) => clk_ms

6:2

MS_DIV_SEL [2:0]

0x0

R/W

division ratio => div = 1/(ms_div_sel + 1)

1:0

MS_SEL[1:0]

0x0

R/W

clkin select (clk_ms)

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

Note: f(clk_ms) = f(clkin) * div;

Table 35 Data Block Output Port (DBOP) Clock Controller Register

Name

Base

Default

CGU_DBOP

AS3525_CGU_BASE

0x00

DBOP Clock Controller Register

Offset: 0x38

This register allows setting the DBOP interface clocks.

Bit

Bit Name

Default

Access

Bit Description

DBOP_EN

R/W

DBOP APB IF clock enable

2:0

DBOP_PREDIV_SEL

[2:0]

0x0

R/W

division ratio => div = 1/(dbop_prediv_sel + 1)

Note:

Setting DBOP_EN will enable both clocks (push/APB and pop) immediately.

clk_dbop clock (pop clock) generation uses DBOP APB IF clock as input clock.

f(clk_dbop) = f(PCLKDBOP) * div;

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