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AS3524 Datasheet(PDF) 52 Page - ams AG |
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AS3524 Datasheet(HTML) 52 Page - ams AG |
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52 / 124 page ![]() AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 52 - 124 Table 32 I2S input status register Name Base Default I2SIN_STATUS AS3525_I2SIN_BASE 0x00 Status register Offset: 0x000C The status register is a read-only register. A read to this register returns the value of the raw status bits AND’ed with the corresponding mask of enable bits set in the mask register. Bit Bit Name Default Access Bit Description 7 stereo24_status 0 R Status of write interface for 24 bit stereo mode 0: left audio sample will be transferred next 1: right audio sample will be transferred next 6 I2SIN_PUER 0 R 1 if FIFO PUSH error 5 I2SIN_POE 0 R 1 if FIFO POP is empty 4 I2SIN_POAE 0 R 1 if FIFO POP is almost empty 3 I2SIN_POHF 0 R 1 if FIFO POP is half full 2 I2SIN_POAF 0 R 1 if FIFO POP is almost full 1 I2SIN_POF 0 R 1 if FIFO POP is full 0 I2SIN_POER 0 R 1 if FIFO POP error Table 33 I2S Input interrupt clear register Name Base Default I2SIN_CLEAR AS3525_I2SIN_BASE 0x00 Interrupt clear register Offset: 0x0010 The interrupt clear register is a write-only register. The corresponding static status bit can be cleared by writing a 1 to the corresponding bit in the clear register. All other interrupt flags are level interrupts depending on the status of the FIFO. The bits are de-asserted depending on the FIFO controller. Bit Bit Name Default Access Bit Description 7 reserved W 6 I2SIN_clear_puer W Clear PUSH error interrupt flag 5:1 reserved W 0 I2SIN_clear_poer W Clear POP error interrupt flag I2SIN_DATA The I2SINIF provides a single 32 bit wide data register. The register is used to read the audio samples from FIFO. If 14 bit mode is selected, both the left and right data are made available in the same register. Otherwise in the 24 bit mode the left and right data are provided through the same register alternatively. The stereo24_status bit in the I2SIN_STATUS register provides information which channel’s data will be provided next. The 14bit_mode bit in the I2SIN_CONTROL register defines how the values are read from the FIFO. |
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