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AS3524 Datasheet(PDF) 48 Page - ams AG |
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AS3524 Datasheet(HTML) 48 Page - ams AG |
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48 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 48 - 124 5.3.7 I2CMSI - I2C master/slave interface This is a general control interface for chip-to-chip communication. The corresponding IOs are either used by the general purpose port C (xpc[6:7]) or by this I2C interface. The features of this interface block are: • serial 2-wire I2C bus master • supports standard (100 kbps) and fast speed (400kbps) • supports multi-master system architecture • programmable clock divider • programmable transfer count • programmable slave wait enable (for slave mode of operation, insertion of wait on the bus) • soft reset bit • interrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received) • status register • test register Figure 22: I2C Interface Table 27 I2C Interface Registers Register Name Base Address Offset Note I2C1_DATA AS3525_I2C_MS_BASE 0x00 transmit/receive FIFO data register I2C1_SLAD0 AS3525_I2C_MS_BASE 0x04 slave ID register 0 I2C1_SLAD1 AS3525_I2C_MS_BASE 0x08 slave ID register 1 I2C1_CNTRL AS3525_I2C_MS_BASE 0x0C control register I2C1_DACNT AS3525_I2C_MS_BASE 0x10 master data count register I2C1_SEAD0 AS3525_I2C_MS_BASE 0x14 self ID of slave 0 I2C1_SEAD1 AS3525_I2C_MS_BASE 0x18 self ID of slave 1 I2C1_CPSR0 AS3525_I2C_MS_BASE 0x1C clock prescale register 0 I2C1_CPSR1 AS3525_I2C_MS_BASE 0x20 clock prescale register 1 I2C1_IMR AS3525_I2C_MS_BASE 0x24 interrupt mask register I2C1_RIS AS3525_I2C_MS_BASE 0x28 raw interrupt status register I2C1_MIS AS3525_I2C_MS_BASE 0x2C masked interrupt status register I2C1_SR AS3525_I2C_MS_BASE 0x30 I2C status register I2C1_TXCNT AS3525_I2C_MS_BASE 0x34 transmit Fifo data count register I2C1_RXCNT AS3525_I2C_MS_BASE 0x38 receive Fifo data count register I2C1_TX_FLUSH AS3525_I2C_MS_BASE 0x3C TX Fifo flush register I2C1_INT_CLR AS3525_I2C_MS_BASE 0x40 interrupt clear register I2C1_TESTIN AS3525_I2C_MS_BASE 0x50 test register (monitors state of SCL and SDA) I2C1_TESTOUT1 AS3525_I2C_MS_BASE 0x54 test mode register for driving output interrupt I2C1_TESTOUT2 AS3525_I2C_MS_BASE 0x58 test mode register for driving SCLout, SCLOEn, SDAOUT and SDAOEN signals |
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