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AS3524 Datasheet(PDF) 36 Page - ams AG |
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AS3524 Datasheet(HTML) 36 Page - ams AG |
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36 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 36 - 124 The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the following. • The system clock • The system clock divided by 16, generated by 4 bits of prescale • The system clock divided by 256, generated by a total of 8 bits of prescale Figure 15 - timer prescaler 5.3.1.2 Interrupt generation An interrupt is generated when the full 32-bit counter reaches zero, and is only cleared when the TimerXClear location is written to. A register holds the value until the interrupt is cleared. The most significant carry bit of the counter detects the counter reaching zero. Interrupts can be masked by writing 0 to the interrupt enable bit in the control register. Both the raw interrupt satus (prior to masking) and the final interrupt status (after masking) can be read from status registers. Timer 1 interrupt output is connected to interrupt input line irq1 (VIC input) and Timer 2 interrupt output is connected to interrupt line irq2. 5.3.1.3 Timer Register Descriptions Table 15 – Timer 1 and 2 registers Register Name Base Address Offset Note Timer1Load AS3525_TIMER_BASE 0x00 load value for Timer 1 Timer1Value AS3525_TIMER_BASE 0x04 current value for Timer 1 Timer1Control AS3525_TIMER_BASE 0x08 Timer 1 control register Timer1IntClr AS3525_TIMER_BASE 0x0C Timer 1 interrupt clear Timer1RIS AS3525_TIMER_BASE 0x10 Timer 1 raw interrupt status Timer1MIS AS3525_TIMER_BASE 0x14 Timer 1 masked interrupt status Timer1BGLoad AS3525_TIMER_BASE 0x18 Timer 1 background load value Timer2Load AS3525_TIMER_BASE 0x20 load value for Timer 2 Timer2Value AS3525_TIMER_BASE 0x24 current value for Timer 2 Timer2Control AS3525_TIMER_BASE 0x28 Timer 2 control register Timer2IntClr AS3525_TIMER_BASE 0x2C Timer 2 interrupt clear Timer2RIS AS3525_TIMER_BASE 0x30 Timer 2 raw interrupt status Timer2MIS AS3525_TIMER_BASE 0x34 Timer 2 masked interrupt status Timer2BGLoad AS3525_TIMER_BASE 0x38 Timer 2 background load value Periheral ID register bits 7:0 AS3525_TIMER_BASE 0xFE0 Peripheral ID register bits 7:0 Periheral ID register bits 15:8 AS3525_TIMER_BASE 0xFE4 Peripheral ID register bits 15:8 Periheral ID register bits 23:16 AS3525_TIMER_BASE 0xFE8 Peripheral ID register bits 23:16 Periheral ID register bits 31:24 AS3525_TIMER_BASE 0xFEC Peripheral ID register bits 31:24 Primecell ID register bits 7:0 AS3525_TIMER_BASE 0xFF0 Primecell ID register bits 7:0 Primecell ID register bits 15:8 AS3525_TIMER_BASE 0xFF4 Primecell ID register bits 15:8 Primecell ID register bits 23:16 AS3525_TIMER_BASE 0xFF8 Primecell ID register bits 23:16 Primecell ID register bits 31:24 AS3525_TIMER_BASE 0xFFC Primecell ID register bits 31:24 |
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