 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AS3524 Datasheet(PDF) 42 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3524 Datasheet(HTML) 42 Page - ams AG |
|
|
42 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 42 - 124 5.3.3 SSP – Synchronous Serial Port The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following: • a Motorola SPI-compatible interface • a TI synchronous serial interface • a National Semiconductor MicroWire interface • In both master and slave configurations the SSP performs • parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep transmit FIFO • serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide, 8 location-deep receive FIFO Interrupts are generated to: • request servicing of the transmit and receive FIFO • inform the system that a receive FIFO overrun has occurred • inform the system that data is present in the receive FIFO after an idle period has expired SSP Features: • compliant to AMBA Rev 2.0 • master or slave operation • programmable clock bit rate and prescale • separate receive and transmit memory buffers each 16 bits wide and 8 bits deep • programmable data frame size from 4 to 16 bit • independent masking of receive FIFO, transmit FIFO and receive overrun interrupts • internal loopback testmode available • support for DMA • identification register uniquely identifying the PrimeCell™ itself (support for OS) SPI features: • full-duplex, four wire synchronous transfer • programmable clock polarity and phase MicroWire features: • half duplex transfer using 8 bit control message Texas Instruments SSI features: • full-duplex, four wire synchronous transfer • transmit data PIN tristateable when not transmitting Programmable parameters: • master or slave mode • enabling of operation • frame format • communication baud rate • clock phase and polarity • data width from 4 to 16 bit • interrupt masking |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
