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AS3524 Datasheet(PDF) 95 Page - ams AG |
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AS3524 Datasheet(HTML) 95 Page - ams AG |
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95 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 95 - 124 Clock Constraining Different clocks are constraint to different maximum clock speeds. As the clock frequencies can be set by software, care must be taken not to exceed these maximum clock frequencies. Table 739 Clock Constraining Clock Domain Max. Freq. [MHz] Description FCLK 250 Processor Clock PCLK 65 AHB/APB bus clock MPMC_CLK 90 MPMC (external memory interface) clock I2SI MCLK 65 I2S input interface master clock I2SO MCLK 30 I2S output interface master clock USB CLK 48 USB interface clock IDE CLK 90 IDE interface clock MS CLK 40 Memory Stick Interface clock Figure 40 Clock Generation Unit Block Diagram |
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