AS3524 datasheet(76/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 57: DBOP status register

bits

Name

type

function

default

value

31:17

reserved

rd_d_valid

read data valid

15:12

Reserved

fi_pu_err

push error

fi_pu_e

push fifo empty

fi_pu_ae

push fifo almost empty

fi_pu_hf

push fifo half full

fi_pu_af

push fifo almost full

fi_pu_f

push fifo full

fi_po_err

pop error

fi_po_e

pop fifo empty

fi_po_ae

pop fifo almost empty

fi_po_hf

pop fifo half full

fi_po_af

pop fifo almost full

fi_po_f

pop fifo full

The read data valid flag is cleared with every start read and set after read data strobe is issued (at read data valid 1 the

data can be readout by SW).

Data Output Register

32 bit register for data output - the data written to this register are directly written to the FiFo. Depending on the serial

output mode and the output data width, the effective register width of this register is 8, 16 or 32 bits.

Following table shows the effective data width for this register:

osm=0

osm=1

osm=2

odw = 0

8 (byte0)

16 (byte0, byte1)

32 (byte0, byte1, byte2, byte3)

odw = 1

16 (HW0)

32 (HW0, HW1)

Depending on odw,

•

either one, two or four bytes are transmitted serially for odw=0

•

or one or two half words (HW = 16 bits) are transmitted serially for odw=1.

Note that for the 8 or 16 bit width only a part of the FiFo memory is used (to keep HW design simple).

Data Input Register

16 bit data input register that holds the value of the last read cycle. It is only valid if the data valid flag is set in the status

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