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AS3524 Datasheet(PDF) 96 Page - ams AG |
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AS3524 Datasheet(HTML) 96 Page - ams AG |
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96 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 96 - 124 5.3.14.5 Clock Generation Unit Registers Table 20 CGU Registers Register Name Base Address Offset Note CGU_PLLA AS3525_CGU_BASE 0x00 PLLA configuration register CGU_PLLB AS3525_CGU_BASE 0x04 PLLB configuration register CGU_PLLASUP AS3525_CGU_BASE 0x08 PLLA supervisor register CGU_PLLBSUP AS3525_CGU_BASE 0x0C PLLB supervisor register CGU_PROC AS3525_CGU_BASE 0x10 processor clock control register CGU_PERI AS3525_CGU_BASE 0x14 peripheral clock control register CGU_AUDIO AS3525_CGU_BASE 0x18 audio clock control register CGU_USB AS3525_CGU_BASE 0x1C USB clock control register CGU_INTCTRL AS3525_CGU_BASE 0x20 CGU interrupt mask and enable register CGU_IRQ AS3525_CGU_BASE 0x24 interrupt clear and lock status register CGU_COUNTA AS3525_CGU_BASE 0x28 PLLA lock counter register CGU_COUNTB AS3525_CGU_BASE 0x2C PLLB lock counter register CGU_IDE AS3525_CGU_BASE 0x30 IDE clock control register CGU_MS AS3525_CGU_BASE 0x34 Memory Stick clock control register CGU_DBOP AS3525_CGU_BASE 0x38 DBOP clock controller register Table 21 CGU_PLLA Register Name Base Default CGU_PLLA AS3525_CGU_BASE 0x00 PLLA Configuration Register Offset0x00 The CGU_PLLA register is used to configure the PLL A Bit Bit Name Default Access Bit Description 14:13 PLLA_OD [1:0] 0x00 R/W PLLA output divider control, 2 bit 12:8 PLLA_R [4:0] 0x00 R/W PLLA input divider control, 5-bit 7:0 PLLA_F [7:0] 0x00 R/W PLLA feedback divider control, 8 bit Table 22 CGU_PLLB Register Name Base Default CGU_PLLB AS3525_CGU_BASE 0x00 PLLB Configuration Register Offset0x04 The CGU_PLLB register is used to configure the PLL B Bit Bit Name Default Access Bit Description 14:13 PLLB_OD [1:0] 0x00 R/W PLLB output divider control, 2 bit 12:8 PLLB_R [4:0] 0x00 R/W PLLB input divider control, 5-bit 7:0 PLLB_F [7:0] 0x00 R/W PLLB feedback divider control, 8 bit |
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