AS3524 datasheet(57/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 36 I2SOUT control register

Name

Base

Default

I2SOUT_CONTROL

AS3525_I2SOUT_BASE

0x0C

Control register

Offset: 0x0000

7 bit wide read/write register containing the control bits of the I2SOUTIF.

Bit

Bit Name

Default

Access

Bit Description

DMA_req_en

R/W

DMA request enable

0: disable

1: enable

sdata_lb

R/W

I2SDATA loopback from I2SINIF

0: I2SOUT_SDATA source is I2SOUTIF’s FIFO

1: I2SOUT_SDATA source is loopback value from I2SINIF

(signal I2SIN_FDATA)

mclk_invert

R/W

Invert MCLK

0: disable (SCLK changes at MCLK’s falling edge)

1: enable (SCLK changes at MCLK’s rising edge)

stereo_mode

R/W

Audio samples provided by processor

0: mono

1: stereo

18bit_mode

R/W

Bit width of audio samples provided by processor

0: 16 bit

1: 18 bit

1,0

osr

R/W

Oversampling rate

00: 128x

01: 256x

10: 512x

11: 128x

CAUTION: The control bit sdata_lb can only be set, if the I2SIN_FSDATA is synchronous to I2SOUT_SCLK. This is the case if AFE is used

together with the AS3525 (in this case the I2SINIF uses also I2SOUT_CLK).

Table 37 I2S Output mask register

Name

Base

Default

I2SOUT_MASK

AS3525_I2SOUT_BASE

0x00

Interrupt mask register

Offset: 0x0004

The interrupt mask register determines which status flags generate an interrupt by

setting the corresponding bit to 1.

Bit

Bit Name

Default

Access

Bit Description

reserved

R/W

stereo18_status cannot assert interrupt request

I2SOUT_MASK_POER

R/W

1 enables the FIFO POP error interrupt

I2SOUT_MASK_PUE

R/W

1 enables the FIFO PUSH is empty interrupt

I2SOUT_MASK_PUAE

R/W

1 enables the FIFO PUSH is almost empty interrupt

I2SOUT_MASK_PUHF

R/W

1 enables the FIFO PUSH is half full interrupt

I2SOUT_MASK_PUAF

R/W

1 enables the FIFO PUSH is almost full interrupt

I2SOUT_MASK_PUF

R/W

1 enables the FIFO PUSH is full interrupt

I2SOUT_MASK_PUER

R/W

1 enables the FIFO PUSH error interrupt

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