AS3524 datasheet(81/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

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Revision 1.11

- 124

5.3.12.5 DIN register

With the dinStrobe, data are written to the DIN register. This gives a simple mechanism, in which for example the status data can be read from a

LCD display interface.

To do a data read, first the START READ (strd) bit is programmed into the control register. With START READ, the control signal generator starts

to generate one cycle with the according control signals. Data are strobed by the programmed strobe time into the din register. After the cycle is

completed the HW resets the strd bit to 0. With set of the strd bit, the rd_data_valid bit is also reseted.

The SW just has to poll the rd_data_valid bit, when the bit gets set the input data can be read from the din register. After read cycle, the control

signal generator returns to the quiescent state.

Following timing diagram shows an example of three read cycles.

Figure 35 DBOP read cycle example

C0 (= read_n)

Data input

Read strobe

Read cycle 0

Read cycle 1

Read cycle 2

DIN register

strd

rd_data_valid

Note: Be aware that the read cycle should only be activated when there is no active write cycle (FiFo is empty). Otherwise the results of such action

get unpredictable.

For any read cycle, the write enable bit must be set to 0 (write disabled).

start read

(strd)

write enable

(wen)

FiFo empty

Status

DBOP function

quiescent

valid write

quiescent

valid read

valid write

quiescent

5.3.12.6 Interrupt Generator

Depending on the FiFo Status, an interrupt request can be generated. The conditions that cause an interrupt are set within the control register.

The interrupt output DBOPIRQ is active high.

AS3524 Datasheet(PDF) 81 Page - ams AG

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