AS3524 datasheet(22/124 Pages) AMSCO

22 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

5.2.4 SMDMAC - Single master DMAC

The ARM PrimeCell™ PL081 “SMDMAC single master DMA controller” is included in the AHB system.

•

AMBA specification Rev 2.0 compliant

•

two DMA channels. Each channel can support a unidirectional transfer

•

provides 16 peripheral DMA request lines

•

single DMA and burst DMA request signals. Each peripheral connected to the PrimeCell™ SMDMAC can assert either a

burst DMA request or a single DMA request. The DMA burst size is set by programming the PrimeCell™ SMDMAC

•

Memory-to-Memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral transfers.

•

Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not

need to occupy contiguous areas of memory

•

Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest

priority and channel 1 has the lowest priority. If requests from two channels become active at the same time the channel

with the highest priority is serviced first.

•

AHB slave DMA programming interface. The PrimeCell™ SMDMAC is programmed by writing to the DMA control registers

over the AHB slave interface

•

One AHB bus master for transferring data. This interface is used to transfer data when a DMA request goes active.

Figure 7 SMDMAC Block Diagram

AS3524 Datasheet(PDF) 22 Page - ams AG