AS3524 datasheet(85/124 Pages) AMSCO

85 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

5.3.13.2 UART Register Descriptions

All registers are 8 bits wide. Registers are selected based on the address and the value of Divisor Latch Select (DLS) bit in the line control register

(UART_LNCTR_REG).

Table 62 UART registers

Base Address

Offset

DLS

Note

UART_DATA_REG

AS3525_UART_BASE

0x00

Data register (Rx / Tx)

UART_DLO_REG

AS3525_UART_BASE

0x00

Clock divider lower byte register

UART_DHI_REG

AS3525_UART_BASE

0x04

Clock divider higher byte register

UART_INTEN_REG

AS3525_UART_BASE

0x04

Interrupt enable register

UART_INTSTATUS_REG

AS3525_UART_BASE

0x08

Interrupt status register

UART_FCTL_REG

AS3525_UART_BASE

0x0C

FIFO control register

UART_LNCTL_REG

AS3525_UART_BASE

0x10

Line control register

UART_LNSTATUS_REG

AS3525_UART_BASE

0x14

Line status register

Table 63 UART Data Register

Name

Base

Default

UART_DATA_REG

AS3525_UART_BASE

0xC8110000

Data register

Offset: 0x00

DLS bit set to 0

Holds the data byte received or the data byte to be transmitted respectively.

RX:

This register holds the received data byte.

In FIFO mode, this byte will be the top byte of the 16-byte FIFO.

If FIFO mode is disabled, it will be the content of the receive shift register after a byte has been

shifted in.

A read to the address value 3b000 with Divisor Latch Select (DLS) bit 1’b0 will give the content of

this register.

If a character less than 8 bits is received, extra zero bits will be padded to this register.

TX:

This register contains the data to be transmitted. This register will be written by the processor.

In FIFO mode, a write to this address will write data into the FIFO.

In FIFO mode, top byte of txFIFO is passed on to transmitter shift register.

If FIFO is disabled, a write to the address 3’b000 with DLS bit 1’b0 will write into this register.

If FIFO is disabled, this register will be overwritten with new data.

If FIFO is disabled, data in this register will be passed on to transmitter shift register.

Bit

Bit Name

Default

Access

Bit Description

7:0

UART_DATA_REG

00000000

Holds the data byte received or the data byte to be transmitted

respectively.

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