AS3524 datasheet(87/124 Pages) AMSCO

87 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 67 UART Interrupt status register

Name

Base

Default

UART_INTSTATUS_REG

AS3525_UART_BASE

0xC8110000

Interrupt status register

Offset: 0x08

This register will give the status of the interrupt. Depending on the enabled interrupt

bits in the interrupt enable register (UART_INTEN_REG) different interrupts will be

generated and the status will be updated in this register. On sensing an interrupt the

software should read this register to get the status of the interrupt.

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

These bits are reserved for future use.

rxLineStatus

This interrupt is set on any error condition on the receive line.

There are four types of error possibilities. These error

conditions are set in bits 4:1 of the line status register

(UART_LNSTATUS_REG).

This bit is reset on a read of the line status register

(UART_LNSTATUS_REG).

txDataEmpty

In FIFO mode this bit is set when txFIFO is empty.

If FIFO mode is disabled this interrupt is set if the data register

(UART_DATA_REG (Tx)) is empty.

This bit will be reset on write to the data register

(UART_DATA_REG (Tx)).

rxDataRdy

This is the data ready interrupt.

In FIFO mode this bit is set when the number of bytes in the

FIFO reaches the trigger level. This bit is also set in FIFO

mode when a timeout occurs in the reception, i.e. Rx line idle

for more than 4 char times and there is data in the FIFO.

If FIFO mode is disabled this bit is set when one full byte is

received.

This bit is cleared when the FIFO is empty or the data register

(UART_DATA_REG (Rx)) is read.

Table 68 UART FIFO control register

Name

Base

Default

UART_FCTL_REG

AS3525_UART_BASE

0xC8110000

FIFO control register

Offset: 0x0C

This register holds the control parameters to control receive (rx) and transmit (tx) FIFO.

The parameters will enable the FIFOs, set the receiver trigger level, etc.

Bit

Bit Name

Default

Access

Bit Description

7:5

Reserved

000

These bits are reserved for future use.

4:3

trigLevel

These two bits will select the trigger level for the rxFIFO. Once

the FIFO pointer reaches this level rxDataRdy interrupt is

asserted.

00: 01 byte

01: 04 bytes

10: 08 bytes

11: 14 bytes

rxFIFORst

This bit will reset rxFIFO pointers and clear all the bytes in the

rxFIFO.

This bit is self clearing, i.e. after resetting FIFO this bit will

become zero.

txFIFORst

This bit will reset txFIFO pointers and clear all the bytes in the

txFIFO.

This bit is self clearing, i.e. after resetting FIFO this bit will

become zero.

FIFOModeEn

This bit will enable the FIFO mode. By default this will be

reset.

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