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AS3524 Datasheet(PDF) 24 Page - ams AG |
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AS3524 Datasheet(HTML) 24 Page - ams AG |
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24 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 24 - 124 5.2.5 Multi Port Memory Controller (MPMC) The MPMC block is integrated into the AMBA system through AHB slave port. The PrimeCell™ MPMC offers: • AMBA 32-bit AHB compliance. • Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM • Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • Single AHB interface for accessing external memory. • 8-bit and 16-bit wide static memory support. • 16-bit wide chip select SDRAM memory support. • Static memory features include: • asynchronous page mode read • programmable wait states • bus turnaround delay • output enable, and write enable delays • extended wait • Two chip selects for synchronous memory and two chip selects for static memory devices. • Software controllable HCLK to MPMCCLKOUT ratio. • Power-saving modes dynamically control SDRAM MPMCCKEOUT and MPMCCLKOUT. • Dynamic memory self-refresh mode supported by software. • Controller supports 2K, 4K, and 8K row address synchronous memory parts. That is typical 512MB, 256MB, 128MB, and 16Mb parts, with 8, 16 bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset. • A separate AHB interface to program the MPMC. This enables the PrimeCell™ MPMC registers to be situated in memory with other system peripheral registers. • Locked AHB transactions supported. • Support for all AHB burst types. Figure 8 Multi Port Memory Controller Block Diagram |
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