AS3524 datasheet(9/124 Pages) AMSCO

9 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

4.2

Operating Conditions

4.2.1 Supply Voltages

Following supply voltages for the digital system are generated by internal LDOs.

Table 2

Operating conditions for internal generated supply voltages

Symbol

Parameter

Min

Max

Unit

Note

VDDperi

3.0

3.6

digital periphery supply voltage

VDDmem

1.75

3.4

digital IO supply for MPMC PADs

VDDcore

1.08

1.25

digital core supply voltage

see Note (1)

VDDcoreana

1.08

1.25

core supply for critical blocks (1-TRAM)

VDDAPLL

1.08

1.25

core supply forPLLA, PLLB

USBVDDA33T

3.15

3.45

USB analog supply transmit block

to be connected to UVDD

USBVDDA33C

3.15

3.45

USB analog supply common block

to be connected to UVDD

Difference of Negative

Supplies

vss_peri, vss_core,

vss_core_ana, vss_mem,

vssa_pll, usb_vssa33c,

usb_vssa33t,

-0.1

0.1

To achieve good performance, the

negative supply terminals should be

connected to low impedance ground

plane.

Note(s)

(1) For the VDD_CORE supply, voltage scaling should be applied to optimize power consumption

and CPU speed performance. For normal operation with fclk (CPU ARM-922T clock) frequencies

below 200 MHz, CVDD (supply of VDD_CORE) can be set to a lower value of 1.10 V. Only for setting

fclk of the CPU to clock frequencies above 200 MHz, the VDD_CORE supply voltage must be set to

1.20 V typical conditions.

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